As is well known, the memory cell of a one time programmable non-volatile memory (also referred as an OTP non-volatile memory) can be programmed once. After the OTP memory cell is programmed, the storage state of the OTP memory cell is determined and the storage state of the OTP memory cell fails to be modified.
Generally, the OTP memory cells may be classified into two types, i.e. a fuse type OTP memory cell and an anti-fuse type OTP memory cell.
Before being programmed, the anti-fuse type OTP memory cell has a high-impedance storage state. After being programmed, the anti-fuse type OTP memory cell has a low-impedance storage state. On the other hand, before being programmed, the fuse type OTP memory cell has a low-impedance storage state. After being programmed, the fuse type OTP memory cell has a high-impedance storage state.
Generally, different types of OTP memory cells have different structures and characteristics. For accurately recognizing the storage states of different types of OTP memory cells, the corresponding read sensing circuits are different.
Please refer to FIGS. 1A, 1B and 1C. FIG. 1A is a schematic circuit diagram illustrating a portion of a conventional anti-fuse type OTP non-volatile memory. FIG. 1B is a flowchart illustrating a read sensing method of the conventional anti-fuse type OTP non-volatile memory of FIG. 1A. FIG. 10 is a sequence diagram illustrating associated signals for the conventional anti-fuse type OTP non-volatile memory of FIG. 1A. The conventional anti-fuse type OTP non-volatile memory is disclosed in U.S. Pat. No. 8,223,526.
As shown in FIG. 1A, the memory array of the conventional anti-fuse type OTP non-volatile memory comprises a precharge circuit 110, OTP memory cells 102 and 104, word lines WL1˜WLi, bit lines BL1 and BL2, isolation transistors 106 and 108, a reference charge circuit REF and a bit line sense amplifier 114. The OTP memory cells 102 and 104 are anti-fuse type OTP memory cells.
The word lines WL1˜WLi are connected with the corresponding OTP memory cells 102 and 104. Moreover, the OTP memory cells 102 and 104 are connected with the bit lines BL1 and BL2, respectively. According to a precharge signal BLPCH, the precharge circuit 110 is controlled to charge the bit lines BL1 and BL2 to a precharge voltage VPCH. According to an enable signal REF_EN, the reference charge circuit REF is controlled to charge the unselected bit line BL1 or BL2 to a reference voltage. Moreover, according to an isolation signal ISO, the isolation transistors 106 and 108 are selectively turned on or turned off. Consequently, the bit lines BL1 and BL2 are coupled with or decoupled from the sense lines SL1 and SL2.
The bit line sense amplifier 114 is operated according to a high logic level enable signal H_EN and a low logic level enable signal L_EN.
As shown in FIG. 1B, the read sensing method comprises the following steps. The process of sensing the OTP memory cell 102 by the bit line sense amplifier 114 is taken as an example. Firstly, in a step 200, the bit lines BL1 and BL2 and the sense lines SL1 and SL2 are precharged to a first supply voltage, i.e. the precharge voltage VPCH. Meanwhile, since the isolation signal ISO has a high logic level, the bit lines BL1 and BL2 are coupled with the sense lines SL1 and SL2 through the on-state isolation transistors 106 and 108.
Then, in a step 202, a selected word line is driven according to a read voltage VREAD. That is, the read voltage VREAD is provided to the word line WL1, but the other word lines WL2˜WLi are not driven. Then, in a step 204, the reference voltage is added to the unselected bit line and the unselected sense line. That is, the bit line BL2 and the sense line SL2 are charged to the reference voltage.
Then, in a step 206, the OTP memory cell is decoupled from the corresponding sense line. That is, according to a low logic level of the isolation signal ISO, the bit lines BL1 and BL2 are decoupled from the sense lines SL1 and SL2 through the off-state isolation transistors 106 and 108. Then, in a step 208, the bit line sense amplifier 114 is activated to sense a storage state of the selected OTP memory cell.
FIG. 1C is a sequence diagram illustrating associated signals for the OTP memory cell 102. It is assumed that the OTP memory cell 102 has a high-impedance storage state.
During the high logic level interval of the precharge signal BLPCH, the isolation signal ISO also has the high logic level. Consequently, the bit lines BL1 and BL2 are coupled with the sense lines SL1 and SL2 are precharged to the precharge voltage VPCH (e.g. a ground voltage).
After the bit lines BL1 and BL2 are coupled with the sense lines SL1 and SL2 are precharged to the precharge voltage VPCH, the word line WL1 and the enable signal REF_EN are enabled. Consequently, the OTP memory cell 102 is a selected memory cell, the bit line BL1 is a selected bit line, and the bit line BL2 is an unselected bit line.
Moreover, during the enabling periods of the word line WL1 and the enable signal REF_EN, the bit lines BL1 and BL2 and the sense lines SL1 and SL2 rise from the precharge voltage VPCH. Since the OTP memory cell 102 has the high-impedance storage state, the rise rates of the selected bit line BL1 and the selected sense line SL1 are lower than the rise rates of the unselected bit line BL2 and the unselected sense line SL2.
At the time point t1, the isolation signal ISO has the low logic level. Consequently, the bit lines BL1 and BL2 are decoupled from the sense lines SL1 and SL2 through the off-state isolation transistors 106 and 108. Meanwhile, the voltage levels of the selected bit line BL1 and the selected sense line SL1 are lower than the voltage levels of the unselected bit line BL2 and the unselected sense line SL2.
At the time point t2, the voltage levels of the bit lines BL1 and BL2 are maintained at the original voltage levels corresponding to the time point t1 because the bit lines BL1 and BL2 are decoupled from the sense lines SL1 and SL2. Moreover, since the bit line sense amplifier 114 is activated, the sense line SL2 with the higher voltage level is increased to the voltage level of the high logic level enable signal H_EN, and the sense line SL1 with the lower voltage level is decreased to the voltage level of the low logic level enable signal L_EN. Since the voltage level of the sense line SL2 is higher than the voltage level of the sense line SL1 after the time point t2, the high-impedance storage state of the OTP memory cell 102 is recognized.
On the other hand, if the voltage level of the sense line SL1 is higher than the voltage level of the sense line SL2 after the bit line sense amplifier 114 is activated, the low-impedance storage state of the OTP memory cell 102 is recognized.
As mentioned above, before the storage state of the OTP memory cell is read, it is necessary to decouple the bit lines from the corresponding sense lines. Then, according to the voltage levels of the sense lines, the storage state of the OTP memory cell can be recognized.
Moreover, U.S. Pat. Nos. 8,259,518 and 7,269,047 also disclose read schemes for reading the storage states of the OTP memory cells with different configurations.